AMD has officially confirmed that its upcoming EPYC “Venice” processor line can be amongst the primary merchandise manufactured utilizing TSMC’s superior 2nm (N2) course of node. This announcement celebrates the long-standing partnership between AMD and TSMC and signifies a serious step ahead in high-performance computing (HPC) know-how. The Venice sequence, primarily based on AMD’s future Zen 6 and Zen 6c architectures, is anticipated to launch in 2026 and can mark a generational leap in CPU design and manufacturing.
In keeping with AMD, the EPYC Venice processors have reached the “tape-out” stage, which means their designs have been finalized and at the moment are prepared to start manufacturing. This milestone positions Venice because the business’s first HPC-oriented chip to succeed in tape-out utilizing the N2 course of. The upcoming EPYC 9006 household will comply with the present EPYC 9005 “Turin” technology and can seemingly debut within the latter half of 2026, following AMD’s typical launch cadence.
✅ Our next-gen EPYC processor, codenamed “Venice,” is the primary HPC product within the business to be taped out and introduced up on the TSMC superior #2nm (N2) course of know-how.
— AMD (@AMD) April 14, 2025
Though AMD has not disclosed detailed specs of the Zen 6 structure, expectations are excessive for vital efficiency good points over Zen 5. Enhancements could embrace elevated core counts and architectural refinements geared toward additional optimizing effectivity and computational energy. These developments will cater to demanding HPC workloads comparable to scientific analysis, simulations, and large-scale knowledge processing.
TSMC’s N2 course of introduces a number of key improvements, most notably the transition to GAAFET (Gate-All-Round Discipline-Impact Transistor) know-how. GAAFETs supply improved management over electrical present, resulting in larger energy effectivity and better transistor density. Moreover, the know-how permits chip designers to fine-tune transistor dimensions for efficiency, energy, or balanced optimization, providing enhanced flexibility in chip engineering.
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#TogetherWeAdvance: Our deep partnership with TSMC is bringing modern applied sciences to market that can energy probably the most demanding knowledge middle functions of the longer term. https://t.co/vFLf3v7JuS pic.twitter.com/a1ilYdKf7S
— AMD (@AMD) April 14, 2025
In one other strategic transfer, AMD has confirmed that its present EPYC 9005 sequence has been validated for manufacturing at TSMC’s Fab 21 facility in Arizona, USA. This manufacturing facility is TSMC’s first within the U.S. and a part of a broader initiative to diversify international semiconductor manufacturing. Fab 21 focuses on 5nm and 4nm processes, and whereas no actual timeline was shared, manufacturing of the EPYC 9005 chips in Arizona is anticipated to start later in 2025, with additional bulletins anticipated.
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